PCIe performance if only a 2-lane PCIe gen3 interface is available

What performance penalty can be expected when interfacing the processor to Hailo 8 via a 2-lane PCIE gen3 interface.
will there be any impact on the Hailo8 core ability? Will 26 TOPS still achievable, or is performance limited to 13 TOPS?

We have to separate several concepts here:

  1. The chip computational performance - measured in TOPS (Terra operations per second)
  2. PCIe bus bandwidth - measured in MBps/GBps (Mega/Giga bytes per second)
  3. Use case performance - measured in fps (frames per second)

The TOPS are not affected by the PCIe bus, so 26 TOPS is achievable regardless of that.
TOPS could be affected for example, by the clock frequency provided to the Hailo chip.

PCIe bus bandwidth is affected by the number of lanes and the PCIe version supported by the host which sets the transfer rate.
Whether it would affect your overall use case performance is depending on your use case requirements (e.g. the model being used, the input stream resolution and fps, number of streams etc.)