Hailo-8L Debug Bus Protocol / Documentation

General
1

Hi,

We are working on bringing up a design with the Hailo-8L connected via PCIe x1.

In our design, we are using the Hailo-8L in PCIe boot mode, with I2S_SDO being pulled up to 1V8.

We have verified

  • All the various voltage sources → as per specification
  • PCIe clock → 100 MHz, diff signal
  • CLKIN → 25 MHz
  • NRESET → 1V8

Unfortunately, we can’t enumerate the Hailo-8L device via PCIe.

We have further exposed GPIO_0, GPIO_4 and GPIO_5 which in various reference designs is labelled as mandatory initial debug bus.

Unfortunately we can’t find any documentation on how the protocol can be used and/or how to interrogate the Hailo-8L over this debug bus.

Any reference would be greatly appreciated.

Thank you, Alex

2

Hey @Alexander_Entinger ,

Welcome to the Hailo Community!

If your Hailo-8L isn’t showing up in lspci, here’s what to check:

Power and Clock Setup

  • Release the reset signal (NRESET) only after power-up is complete
  • Ensure both clocks are stable first: 100 MHz PCIe clock (REFCLK) and 25 MHz clock (CLKIN)
  • Confirm I2S_SDO is pulled up to 1.8V for PCIe boot mode

Debug Pins The GPIO pins (GPIO_0, GPIO_4, GPIO_5) are for internal factory testing only - treat them as generic I/O.

If Problems Persist

  • Use SCU recovery mode to boot from alternate source and reload firmware
  • Verify reset and clock timing (PCIe devices are timing-sensitive)
  • Enable PCIe link training on your host

Bottom Line: This is typically a timing issue with power, clocks, or reset signals rather than hardware failure.

3

Hi @omria :coffee: :waving_hand:

We’ve verified power and clock setup, as well as power/reset/clock timing and could not determine any deviations. I2S_SDO is pulled up too.

Is there any other way to determine if the Hailo-8L is coming up and running, i.e. by interrogating its JTAG interface, even when running in PCIe boot mode?

Do you have additional information about the SCU recovery mode?