Hey we are trying to get Hailo 8L accelerator on NXP i.MX6 platform. I suppose there is no official support for 32 Bit platform but I still tried. I used the the scarthgap release of meta-hailo and did encounter compiler error.
Claude was able to fix the errores with minor patches, and the build succeeded. I wanted to ask weather these patch is fine or will cause issues.
Following for pcie driver
From: SightForge Build <build@sightforge.co>
Date: Sun, 13 Jul 2026 00:00:00 +0000
Subject: [PATCH] fix 32-bit ARM build errors in hailo-pci driver
On 32-bit ARM (iMX6 Cortex-A9), dma_addr_t is u32 (no LPAE) so the
declaration in vdma_common.h conflicts with the u64 in the implementation.
Also size_t is unsigned int on 32-bit so %lx format is wrong; use %zx.
---
--- a/common/vdma_common.h 2026-07-13 11:24:11.286006686 +0530
+++ b/common/vdma_common.h 2026-07-13 11:24:11.289006649 +0530
@@ -182,7 +182,7 @@
channel, channel_index)
void hailo_vdma_program_descriptors_in_chunk(
- dma_addr_t chunk_addr,
+ u64 chunk_addr,
unsigned int chunk_size,
struct hailo_vdma_descriptors_list *desc_list,
u32 starting_desc,
--- a/linux/vdma/ioctl.c 2026-07-13 11:24:11.287006673 +0530
+++ b/linux/vdma/ioctl.c 2026-07-13 11:24:11.291006624 +0530
@@ -250,7 +250,7 @@
return -EINVAL;
}
- hailo_dev_dbg(controller->dev, "mapping buffer <0x%lx + 0x%lx> tgid: %u\n",
+ hailo_dev_dbg(controller->dev, "mapping buffer <0x%lx + 0x%zx> tgid: %u\n",
params.addr_or_fd, params.size, current->tgid);
buffer = find_buffer(context, params, direction);
@@ -304,11 +304,11 @@
return -EINVAL;
}
- hailo_dev_dbg(controller->dev, "unmap user buffer <0x%lx + 0x%lx>\n", params.addr_or_fd, params.size);
+ hailo_dev_dbg(controller->dev, "unmap user buffer <0x%lx + 0x%zx>\n", params.addr_or_fd, params.size);
buffer = find_buffer(context, params, direction);
if (NULL == buffer) {
- hailo_dev_warn(controller->dev, "buffer <0x%lx + 0x%lx> not found\n", params.addr_or_fd, params.size);
+ hailo_dev_warn(controller->dev, "buffer <0x%lx + 0x%zx> not found\n", params.addr_or_fd, params.size);
return -EINVAL;
}
Userspace libraries
From: SightForge Build <build@sightforge.co>
Date: Sun, 13 Jul 2026 00:00:00 +0000
Subject: [PATCH] fix 32-bit ARM: cast return to size_t in get_async_queue_size
Expected<T>(T&&) requires an rvalue. On 64-bit, returning uint32_t into
Expected<size_t> (where size_t=u64) produces an implicit widening conversion
creating a temporary rvalue. On 32-bit ARM size_t==uint32_t so no conversion
occurs, leaving a const lvalue that cannot bind to T&&. Add explicit cast.
---
--- a/hailort/libhailort/src/net_flow/pipeline/configured_infer_model_hrpc_client.cpp 2026-07-13 11:47:25.667625591 +0530
+++ b/hailort/libhailort/src/net_flow/pipeline/configured_infer_model_hrpc_client.cpp 2026-07-13 11:47:25.668625579 +0530
@@ -442,7 +442,7 @@
Expected<size_t> ConfiguredInferModelHrpcClient::get_async_queue_size() const
{
- return m_max_ongoing_transfers;
+ return static_cast<size_t>(m_max_ongoing_transfers);
}
hailo_status ConfiguredInferModelHrpcClient::validate_bindings(const ConfiguredInferModel::Bindings &bindings)
Is this fine or any other recommended way to use it with 32bit platform