I connected Heilo via pcie with a zynq ultrascele mpsoc processor. I have provided a reference clock of 100 MHz and I have PRESET signal. The clock only comes when I load the bitstream and device-tree overlay of my project. I see only with lspci PCI bridge Xilinx Corporation. Can I find the power sequence timing somewhere and is it necessary for Heilo to have a reference clock when it receives power? When booting the board, does that clock of 100 MHz have to exist or can the clock be added later, the PRESET is reset and the pci bus is rescanned.
Hey @sara_kuljanin,
Welcome to the Hailo Community! Great to have you here.
So about your power sequencing questions - let me break this down for you:
Power-Up Sequence
You’ll need to follow a specific order when powering up the Hailo device. Start by asserting NRESET, then bring up VDDIO (1.8V), followed by VDD_CORE (0.8–0.83V). After that, you can power the PCIe supplies in any order. The reference clock should come on after VDDIO has stabilized, and you’ll want to wait until the clock has been stable for at least 10 cycles before de-asserting NRESET.
Timing-wise, here’s what you need to watch for:
- Wait at least 1 μs between VDDIO and VDD_CORE
- Another 1 μs minimum from VDD_CORE to PCIe supplies
- Give it at least 1 ms from VDDIO to when your clock is stable
- Wait 100 μs minimum after clock stabilization before releasing RESET_N
- The total time from VDDIO to RESET_N de-assertion shouldn’t exceed 70 ms
You can find the full timing diagrams in Section 4.3 of the Hailo-8L datasheet or Section 3.3 for Hailo-8/10H in the developer zone.
Clock Requirements
This is important - you absolutely need that 100 MHz reference clock up and running before you de-assert NRESET. The clock needs to be stable and meeting all the CLK_IN specs for proper PCIe initialization to work. Check the Power-up Sequence section in your device’s datasheet for the detailed clock specifications.
About Adding Clock After Power-Up
Unfortunately, adding the reference clock after initial power-up and trying to rescan the PCIe bus isn’t going to work. The device really needs that clock present before it exits reset for PCIe enumeration to happen correctly. If your clock isn’t there during initial power-up (like if you’re loading it through an FPGA bitstream), the PCIe initialization will fail and the device won’t show up in lspci.
For all the detailed specs and device-specific requirements, check out the datasheet and Board Design Guidelines for your Hailo model in the developer zone.
Let me know if you have any other questions!